side_1#
- class ansys.fluent.core.generated.solver.settings_251.side_1(name=None, parent=None)#
Bases:
String,AllowedValuesMixinEnter id/name of zone to convert to phase lag side 1.
Included in:
Parent |
Summary |
|---|---|
Make interface zones phase lagged. |
Bases: String, AllowedValuesMixin
Enter id/name of zone to convert to phase lag side 1.
Included in:
Parent |
Summary |
|---|---|
Make interface zones phase lagged. |